Given that the target audience is predominantly SW-engineering focused, a reasonable starting point would be to discuss the time domain differences if compared to HW-engineering. Software is inherently serial, if you have a set of entities – those entities will be dealt with serially in separate instances of time. Hardware view is much more parallel – a set of entities will be dealt with at the same instance of time, even if there are dependencies among those entities. This difference in viewpoints often is the limiting factor in trying to switch the brain from SW to HW engineering mode. Then it is time to introduce combinational and sequential logic, a concept of state machine and its equivalence to memory-backed variable in sw domain, and then move to deeper aspects of internal FPGA functional blocks. An important aspect to mention is that even if one sees an FPGA as an unordered set of logical elements, it is not a direct equivalent of sea of К155ЛА3/7400 gates, and soldering a capacitor to an FPGA directly would not result in an equivalent of a clock generator.

Discussing the underlying LUT plus fixed logic elements and their interconnections should be done in the context of what could be mapped to FPGA-based designs easily, and what would be hard to achieve, with some quantization of what ‘hard’ and ‘easy’ mean here and in what dimensions they are measured. Having much of the focus and time on hardware description DSLs might not be too practical – at the end that is just a tool to express for expressing the intent, and the intent is mostly constrained by how well it maps onto the FPGA structure, and much less depends on the specifics of the DSL. If the intention is to touch the ASIC topic, it seems reasonable to address the differences in logical and physical HW implementation layers – the soft and hard functional components (ie, you can implement a processor core based on the logical elements of the FPGA itself or use a separate fixed structure core provided as a separate logical element – both having exactly same ISA and external behavior characteristics, but a vastly different performance), and library vs custom based topology components for ASIC layout – again, the discussion of performance characteristics and the quantization of dimensions of those characteristics. A good subtopic to mention would be on the industry trends and why FPGA-derived programmable logic structures are becoming more relevant in the context of generic compute platforms.

An important observation is that an FPGA does not operate in isolation – it has external interfaces to other components, and a large part of complexity related to system level design comes particularly from the specifics of those interfaces.